Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic elements (CLEs) and programmable input/output blocks (IOBs). A CLE typically includes programmable logic elements such as function generators, memory elements (e.g., flip-flops), and so forth. The CLEs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, processors, and so forth).
The interconnect structure, CLEs, IOBs, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
Note that the term PLD as used herein is not limited to FPGAs and CPLDs. However, FPGAs are used as examples of PLDs to which the structures and methods of the invention can readily be applied.
One type of FPGA, the Xilinx Virtex® FPGA, is described in detail in pages 3–75 through 3–96 of the Xilinx 2000 Data Book entitled “The Programmable Logic Data Book 2000”, published April, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) Young et al. further describe the interconnect structure of the Virtex FPGA in U.S. Pat. No. 5,914,616, issued Jun. 22, 1999 and entitled “FPGA Repeatable Interconnect Structure with Hierarchical Interconnect Lines”, which is incorporated herein by reference in its entirety.
As was briefly mentioned above, advanced FPGAs can include several different types of logic blocks in their programmable arrays. For example, in addition to CLEs and IOBs, the Xilinx Virtex®-II FPGA includes blocks of Random Access Memory (RAM) and digital clock manager (DCM) blocks. (The Xilinx Virtex-II FPGA is described in pages 33–75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., which pages are incorporated herein by reference.) The Xilinx Virtex-II Pro™ FPGA also includes embedded processor blocks. (The Xilinx Virtex-II Pro FPGA is described in pages 19–71 of the “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002 and available from Xilinx, Inc., which pages are incorporated herein by reference.) Some of these FPGAs also include other types of logic blocks.
FPGA interconnect structures are typically very complex, and can include hundreds of thousands of programmable interconnect points (PIPs) that control the interconnections among the interconnect lines and between the interconnect lines and the other elements in the device. Because the user circuit to be implemented in an FPGA is unknown at the time of testing, a user design might make use of any of these PIPs and interconnect lines. Therefore, ideally every PIP and every interconnect line is tested during the FPGA production process. There can be exceptions, which might include, for example, PIPs included in the device that are not accessible to the design software and that will therefore never be used. However, the vast majority of PIPs and interconnect lines should be tested. Clearly, the testing procedure can be a time-consuming and expensive process, significantly impacting the production cost and thus the sales price of the FPGA.
Therefore, it is desirable to provide structures and methods that simplify the testing process for programmable interconnect structures in PLDs.